Device Support Summary For "Infineon(Siemens) IRPS5401MTRPBF"

 
Generated by:BPWin V7.0.7 DeviceSupportUpdate.72 (11/30/2021)
 
Device Parameters

Manufacturer:Infineon(Siemens)
Part Number:IRPS5401MTRPBF
8-bit Bytes:131072
Memory Regions:0h-1 FFFFh
Vcc(program):5.0
Packages:QFN(56)
 
Note

IMPORTANT:
Device Type: Infineon Flexible Power Management Unit
Device Memory Type: Configuration Registers
Algorithm Programming Method: PMBus
Supported Data File Format: Single image three column configuration file
Serialization Supported: No

Memory Organization:
Memory Type

Attributes(*)

Included in default
Range (Y/N)
DUT Physical Byte Address(hex)
(if this area is selected/Activated)
BPWin Buffer Byte Address(hex)
Configuration Registers R/W/E Yes 0000 - 17FF Determined by data file
Default Algorithm Range --- --- 0000 - 17FF Determined by data file
* R/W/E: readable and rewritable if not locked.
Configuration Register Mapping:
Section Switcher Register Range(hex) Enable Register(hex) and Bit
CNFG --- 0000 - 0001 ---
User Common 0020 - 003A ---
User A 0420 - 043F
0600 - 06FF
0700 - 07FF
0038[0]
User B 0820 - 083F
0A00 - 0AFF
0B00 - 0BFF
0038[1]
User C 0C20 - 0C3F
0E00 - 0EFF
0F00 - 0FFF
0038[2]
User D 1020 - 103F
1200 - 12FF
1300 - 13FF
0038[3]
User LDO 1420 - 143F
1600 - 16FF
1700 - 17FF
0038[4]

Special Device Considerations:
1. Programming each section (CNFG, User) can be enabled or disabled
for Program and Verify operations under Device->Settings.
2. The CNFG section is limited to five image writes.
If the CNFG section is enabled and there are no more write attempts, the Program operation will fail.
3. The User section is limited to 26 image writes.
If the User section is enabled and there are no more write attempts, the Program operation will fail.
4. The CNFG section should be programmed at least once.
Otherwise, the User section may not verify correctly.
5. This algorithm will only program and verify the register ranges
listed in the Configuration Register Mapping table above.
The masks in the data file will determine which bits to verify.
6. By default, all switcher registers will be verified. If register 0038h is specified in the data file,
the data there will be used to determine which switcher registers to verify.
See the Configuration Register Mapping table above for which bit corresponds to which switcher.
A bit value of 0b will enable that switcher, and 1b will disable it.
7. Operations on the TRIM section are not supported.
8. Check MTP operation checks how many writes are left in the USER/CNFG sections.
 
= Supported
 
= This is a replacement daughter card that requires a base socket module
 
Automated Production Programmers

Programmer Model:390049003710-MK24710
Algorithm Code Revision:1.21.21.21.2
 
QFN Socket Modules (Sorted by Performance)
FX4ASMR56QFNK   
ASMR56QFNK   
LX4ASMR56QFNK     
 
Manual Production Programmers

Programmer Model:190029002710
Algorithm Code Revision:1.21.21.2
 
QFN Socket Modules (Sorted by Performance)
FX4ASMR56QFNK   
ASMR56QFNK   
LX4ASMR56QFNK   
 
Engineering Programmers

Programmer Model:1710
Algorithm Code Revision:1.2
 
QFN Socket Modules (Sorted by Performance)
FX4ASMR56QFNK
ASMR56QFNK
LX4ASMR56QFNK   
 
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Last Updated: 01/14/2021