IMPORTANT:
Device Type: | Flash Memory |
Device Size: | 64 Mbit |
Algorithm Programming method: | Standard Single SPI |
Memory Organization:
Memory Type |
Attributes(*) |
Included in default Range (Y/N) |
DUT Physical Byte Address(hex) (if this area is selected/Activated) |
BPWin Buffer Byte Address(hex) |
Main Flash Area |
R/W/E |
Yes |
0000_0000 - 007F_FFFF |
0000_0000 - 007F_FFFF |
SecSi sector |
R/W |
No |
0080_0000 - 0080_03FF |
0080_0000 - 0080_03FF |
| | | | |
Default Algorithm Range |
--- |
--- |
0000_0000 - 007F_FFFF |
0000_0000 - 007F_FFFF |
* R:Read only, W:One time programmable (OTP), R/W:readable and one time programmable (OTP), R/W/E:readable and rewritable if not locked.
Any configurations listed under "Device-Specific" in the menu item Device-> Settings will be written to the DUT during "Program" operation regardless of memory range selection.
Special Device Considerations: |
|
Configuration Register 3 (CR3NV) is not supported in this algorithm.
Configuration Register 2 (CR2NV) only supports programming the IO3_Reset and Output Impedance bits.
Erase must be selected if device to be programmed already has QE bit enabled.
There are four 256-Byte Security Registers with OTP locks independent from main memory.
mapped to[800000-8000FF],[800100-8001FF],[800200-8002FF],[800300-8003FF] in the Data Pattern respectively.
Lock bits LB[3:0] are onetime programmable(OTP). | |